1. Field of the Invention
The present invention relates to a method of fabricating a heterojunction semiconductor device, and more specifically, to a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT).
2. Discussion of Related Art
In general, a pseudomorphic high electron mobility transistor (PHEMT), which is a compound semiconductor device, includes material layers having quite different lattice constants so that a channel layer is structurally transformed due to this lattice mismatch. As a result, it is difficult to have layers grown on a substrate during the fabrication process of the PHEMT. Nevertheless, since the PHEMT has a high density of charges to transfer to the channel layer and high electron mobility, the PHEMT has better power and noise characteristics than conventional devices have. Accordingly, the PHEMT can operate in a high frequency range and has higher electron speed characteristics than devices using silicon have so that it can be widely used for micro- or millimeter-band devices. In particular, because the PHEMT has a good ultrahigh-frequency noise characteristic, the PHEMT can accelerate the developments of high-performance millimeter-band wireless-communication circuits and components and optical-communication circuits and components exceeding several tens of Gbps.
A high-speed device should have a short gate length for high modulation and a wide gate sectional area enough to lower resistance for good noise characteristics. To meet these requirements, a T-shaped gate or a mushroom-shaped gate has lately been employed. Typically, the T-shaped gate or the mushroom-shaped gate may be formed by an electron beam (e-beam) lithography process or a photolithography process. However, the photolithography process has a specific resolution limit in forming a gate electrode having a fine linewidth. Accordingly, a gate electrode is usually formed through the e-beam lithography process.
FIG. 1 is a cross-sectional view illustrating a method of fabricating a conventional PHEMT, which schematically shows a PHEMT using a substrate of AlGaAs/InGaAs/GaAs according to U.S. Pat. No. 6,242,293 filed on Nov. 18, 1998.
A channel layer 2 including a dimensional electron gas (DEG) layer, an AlGaAs spacer layer 3, a Si delta-doping layer 4, an n-AlGaAs layer 5, an etch stop layer 6, an n-GaAs layer 7, and a GaAs capping layer 8 are formed on a semi-insulating GaAs substrate 1 including predetermined layers, and a source electrode 9 and a drain electrode 10 are formed on the GaAs capping layer 8.
A photoresist layer (not shown) is formed on the entire surface of the resultant structure and then patterned, thereby forming a photoresist pattern. Then, the GaAs capping layer 8 and the n-GaAs layer 7 are patterned by an etching process using the patterened photoresist as an etching mask to expose the etch stop layer 6 in a channel region, so that a double recess structure is formed.
Thereafter, a metal layer is deposited on the entire surface of the resultant structure to fill the double recess structure, and the metal layer is patterned by an etching process using a predetermined photoresist pattern as an etch mask. Thus, a gate electrode 11 is formed such that the gate electrode 11 is connected to the etch stop layer 6 through the double recess structure.
However, in the above-described method, since the double recess structure is formed by a wet etching process, it is difficult to accurately control the linewidth of the gate electrode 11 due to etching of the lateral surfaces of the GaAs capping layer 8 and the n-GaAs layer 7. Also, an active region is exposed and oxidized so that the electrical characteristics of the PHEMT are degraded. Furthermore, an undercut is formed during the etching of the substrate, and thus the length of the gate electrode 11 increases and a source resistance increases. These problems deteriorate the electrical characteristics of the PHEMT and preclude high integration of the PHEMT.